YuLong DAART Aquila II DAC Amplifier
Apr 12, 2020 at 10:37 AM Post #16 of 100
On the Shenzhenaudio link it says:
"Double-loop cattle multi-group multi-stage linear power supply"

My the best guess is as follow:
Double-loop cattle = double shielded toroidal transformer
multi-group = dual "Double-loop cattle"

So this bubble translation should read:
Dual double shielded toroidal transformers and multi-stage linear power supply.

If wrong, my Chineese is better than my English. :smile_phones:
 
Apr 12, 2020 at 6:04 PM Post #17 of 100
Hi, 80% internal components looks same as DA10, except the chip and power supply, how is it that it is so cheaper?
But actually I would rather like to see DA10 at that price :) A already have 9038 dac/amp based device.

DA10 down here
1586729007533.png
 
Apr 16, 2020 at 3:41 AM Post #19 of 100
Hi, 80% internal components looks same as DA10, except the chip and power supply, how is it that it is so cheaper?
But actually I would rather like to see DA10 at that price :) A already have 9038 dac/amp based device.

DA10 down here

We have migrated our JIC (Jitter and Interface control) technology from DA10 to Aquila II, that's the major similarity between Aquila II and DA10, but the power supply and headphone amplifiers circuit are completely different. DA10 is fully discrete JFET input Class A amplification and Aquila II is IC based Class AB. On paper Aquila II has higher power rating, but Class A offer better control and transient, and a more appealing sound signature. Because of that, the DA10 needs a stronger power supply in order to keep the discrete components to operate in saturated capacity. All these added up to extra costs between Auqila II and DA10.
 
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Apr 16, 2020 at 3:50 AM Post #20 of 100
On the Shenzhenaudio link it says:
"Double-loop cattle multi-group multi-stage linear power supply"

My the best guess is as follow:
Double-loop cattle = double shielded toroidal transformer
multi-group = dual "Double-loop cattle"

So this bubble translation should read:
Dual double shielded toroidal transformers and multi-stage linear power supply.

If wrong, my Chineese is better than my English. :smile_phones:

Interesting, you are based in South Africa but your Chinese is better than your English.

I believe that is a automated translation from our Chinese description: 双环牛多组多级线性电源供电

We have rewritten our product description in English, check the link in my signature and hopefully that'll clarify the misleading translation.
 
Apr 16, 2020 at 7:28 AM Post #21 of 100
Interesting, you are based in South Africa but your Chinese is better than your English.
Well, it is the worst compliment I could ever heard. In the mouth of the pure Englishman such remark is only used to express negatively the overall quality of the person, not just a language skills. I know, you wanted it to look funny.
:L3000:

I saw a new product description and I must say, implementation of the DAC looks very solid. I like especially a choice between the ESS ASRC mode and a synchronous mode. A synchronous mode can be confusing for those who only look from the USB transfer mode point of view. You made it clear, it is about bypasing the internal resampler of the ESS chip. In this mode a DAC is still using a local precise Femtosecond oscilators for FIFO clock recovery and PLL. This jitter control looks very sophisticated, more details would be welcome. One thing is clear: there is no resampler in the FPGA, DA conversion is made in the ESS chip at a source sample rate. That's briliant!

Do you use digital filtering of data in the FPGA or it is done as usual in the ESS chip?
 
Apr 16, 2020 at 12:45 PM Post #22 of 100
Well, it is the worst compliment I could ever heard. In the mouth of the pure Englishman such remark is only used to express negatively the overall quality of the person, not just a language skills. I know, you wanted it to look funny.
:L3000:

I saw a new product description and I must say, implementation of the DAC looks very solid. I like especially a choice between the ESS ASRC mode and a synchronous mode. A synchronous mode can be confusing for those who only look from the USB transfer mode point of view. You made it clear, it is about bypasing the internal resampler of the ESS chip. In this mode a DAC is still using a local precise Femtosecond oscilators for FIFO clock recovery and PLL. This jitter control looks very sophisticated, more details would be welcome. One thing is clear: there is no resampler in the FPGA, DA conversion is made in the ESS chip at a source sample rate. That's briliant!

Do you use digital filtering of data in the FPGA or it is done as usual in the ESS chip?

Well, I am nothing close to a pure Englishman. I am a native Chinese based in HK, sorry if I offended you, and that's why I am interested to find out whether you are a Chinese living in South Africa, or a native South African mastering Chinese language which, IMHO, is not easy to come by. Sorry if I didn't get the tone right.

The ASRC in ESS is an important strength to some, but the root of digital artifacts to others, and we are glad to have this option to bypass it in ES9038Pro. We didn't have that option in previous ESS DAC chipset, so we decided to give it a try when we have the chance. We have the exact worry when we try to name this feature, we sure don't want to confuse with Asynchronous USB Transmission terminology, that's why we call it Digital Processing Circuit and only introduce the concept of synchronous and asynchronous in the detail description.

The high precision low noise JIC (Jitter and Interface Control) is the accumulation of YuLong's experience in digital audio product development. It was partially implemented in DA9 and introduced for the first time in DA10. We have a brief introduction of the JIC technology in the branding statement HERE. I didn't have the technical background to explain the JIC in further details, but if you have any specific question, I can bring it to YuLong, ask him to draft a response in Chinese, and then translate to English with my finger crossed.

There are three digital filters in Aquila II:
  • PHASE: equivalent to minimum phase fast-roll off filter in ESS
  • SHARP: equivalent to fast roll -off, linear phase filter in ESS
  • SLOW: equivalent to slow roll -off, linear phase filter in ESS
By the way, to avoid confusion, YULONG is a brand, YuLong is a person, the founder of YULONG Audio. :beerchug:
 
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Apr 16, 2020 at 3:49 PM Post #23 of 100
Thanks for this update. I am a new member and I missed that JIC was introduced first time in DA10. I am not Chineese, not reading a single logogram, but I remember that someone else on Aliexpress tried to sell me equipment with a double-loop cattle. :)

I am fascinated with the old Chineese culture, it is so important to the people that even communist system didn't manage to destroy it! Mr YouLong must be an audioholic passionate, hats off guys!

No, you didn't offend me, but I do notice that your English is better than mine. Well that's a life. :frowning2:



YuLong
 
May 30, 2020 at 11:38 PM Post #24 of 100
I know the Zeos review is out soon and hopefully he can actually describe how it sounds LOL.
 
May 31, 2020 at 1:30 AM Post #25 of 100
I have it in for review, several things ahead of it though.

Quick first impression - as a DAC It sounds remarkably similar to the Yulong DA10, which is a very good thing. That means neutral and clean but also a somewhat sweet tonality and very analog feeling. The headphone stage is a step down from the fully discrete DA10 but still quite capable considering the price. Build quality and general feel/appearance is beyond anything I've experienced for $700.

Much more to come when I have the time.
 
Jul 8, 2020 at 11:43 PM Post #28 of 100
Here pls refer to the Aquila II review from ZReviews.
 
ShenzhenAudio https://twitter.com/shenzhenaudio Stay updated on ShenzhenAudio at their sponsor profile on Head-Fi.
 
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Jul 9, 2020 at 11:45 AM Post #29 of 100
Here pls refer to the Aquila II review from ZReviews.


Any chance of sending it to a reviewer who knows about sound and technical specs?

Just kidding it was actually a good review lol!
 
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